In June 2026, OpenAI and Broadcom unveiled Jalapeño, a custom inference ASIC taped out in nine months. Two weeks later, on July 7, Reuters reported that DeepSeek—the Chinese lab behind R1 and V4—is quietly developing its own inference-only AI chip, citing three people familiar with the matter. The counter-intuitive detail: DeepSeek already runs on Huawei Ascend, yet still pursues in-house silicon. Co-design partnerships and internal R&D are running in parallel; custom chips remain early, partnerships are live.
This article is for developers, infra investors, and CTOs tracking AI unit economics and supply-chain risk. We synthesize Reuters, WSJ, OpenAI official posts, Waves interviews, and Alibaba earnings to cover: the global July 2026 chip wave, DeepSeek evidence and timeline, what DeepSeek CEO Liang Wenfeng has (and has not) said, Alibaba T-Head mass production, five drivers behind custom silicon, inference vs training, risks, five FAQ answers, and a six-step action framework.
Last updated: July 9, 2026. DeepSeek has not officially confirmed the chip project as of this writing.
01 This Is Not Just China: OpenAI Jalapeño and the Global Custom Chip Wave
Pain points for infra teams:
- The Nvidia tax: Data-center GPU gross margins exceed 70%. At hyperscaler scale, inference is recurring rent, not a one-time capex.
- Allocation risk: Even US cloud giants face GPU rationing. Custom ASICs are negotiating leverage, not just nationalism.
- Workload mismatch: General GPUs are Swiss Army knives; LLM inference is a single, predictable workload—ASICs win on unit economics.
- Speed of the trend: TrendForce (2026): custom AI chip shipment growth at 44.6% vs 16.1% for general GPUs—custom silicon is outpacing GPUs for the first time on growth.
Dense July 2026 headline cluster:
- 2026-06-24: OpenAI + Broadcom Jalapeño inference ASIC (9-month tape-out)
- 2026-07-02: Anthropic reportedly in talks with Samsung on 2nm custom silicon
- 2026-07-07: Reuters: DeepSeek developing inference chip
- 2026-07-07: The Information: Zhipu AI evaluating custom chips
| Company | Project | Stage | Workload | Key signal |
|---|---|---|---|---|
| OpenAI | Jalapeño (Broadcom) | Tape-out done | Inference | Deploy late 2026; ~50% cost savings claimed |
| TPU v6/v7 | At scale | Train + infer | Gemini end-to-end on TPU | |
| Amazon | Trainium3 / Inferentia | Commercial | Both | Anthropic on Trainium at scale |
| Microsoft | Maia 100 | Deploying | Inference | Azure / OpenAI workloads |
| Meta | MTIA | Internal | Inference | Recommendations; one redesign already |
| Anthropic | Samsung talks | Exploratory | TBD | The Information, July 2026 |
| DeepSeek | Unnamed inference ASIC | Early R&D | Inference | $7.4B round; no official confirm |
| Alibaba (T-Head) | Zhenwu 810E / M890 | Mass production | Train + infer | 560K+ units shipped; billion-yuan revenue |
| Huawei | Ascend 950 | Mass production | Both | DeepSeek V4 adapted; orders surging |
| Zhipu AI | Custom chip eval | Early | Inference | The Information, July 2026 |
02 What Reuters Actually Reported (And What DeepSeek Has Not Confirmed)
On July 7–8, 2026, outlets followed Reuters with consistent facts:
- DeepSeek is building a custom AI chip for inference, not training.
- The program started around mid-2025 (~one year ago) and remains early stage.
- DeepSeek is talking to chip designers, foundries, and memory suppliers.
- Chip engineers are being hired privately—not via public job boards.
- Success would reduce dependence on both Nvidia and Huawei Ascend.
| Dimension | Assessment |
|---|---|
| Source tier | High — Reuters standard "three people familiar with the matter" |
| Official confirmation | None as of research date |
| Circumstantial evidence | Strong — ~$7.4B external round (June 2026) citing custom chips; IDC hiring; UE8M0 FP8 format read as hardware-software co-design |
| Contradictory takes | Some analysts say near-term reliance on Ascend grows. Accurate framing: partnership and in-house R&D in parallel |
Write "Reuters reports DeepSeek has launched an inference chip program." Do not write "Liang Wenfeng officially announced chip production." Tag: sources / early stage / unconfirmed.
| Date | Milestone |
|---|---|
| 2023–2024 | Liang Wenfeng Waves interviews: export bans, compute hunger |
| 2025-01 | DeepSeek R1 on Nvidia H800 (export-banned since late 2023) |
| Mid-2025 | Chip program reportedly starts |
| 2026-04 | V4 adapted to Ascend; V4-Flash partial Ascend training |
| 2026-06 | ~$7.4B funding round; custom chips in disclosed use of funds |
| 2026-07-07 | Reuters exclusive on inference ASIC |
03 What DeepSeek CEO Liang Wenfeng Has Said — and Alibaba T-Head Is Already Shipping
Liang Wenfeng rarely speaks publicly. The best sources are two Waves interviews (May 2023, July 2024). He has never announced a DeepSeek chip program. Reuters describes company behavior—hiring, supplier talks—not a founder launch event.
Four Liang quotes on chips and compute:
- Export bans, not money: "Our real challenge has never been funding—it is export controls on advanced chips." (July 2024)
- ~4× compute gap: Domestic training and data efficiency each lag ~1×; combined you need roughly 4× compute for the same result.
- Tech frontier: Domestic chips lack a developer community; China needs teams at the frontier, not second-hand information.
- Compute appetite: Researchers' hunger for compute is endless—we deploy as much capacity as we can.
Alibaba T-Head: eight years of execution, not a fresh rumor. Jack Ma named Pingtouge (T-Head) at the September 2018 Apsara conference, merging Damo Academy and C-SKY teams. Chairman Joe Tsai (2024 podcast) tied export controls to cloud strategy; CEO Wu Yongming (FY2026 earnings) disclosed 470K+ AI chips delivered and billion-yuan annualized chip revenue.
| SKU | Timing | Highlights |
|---|---|---|
| Hanguang 800 | 2019 | Early inference ASIC |
| Zhenwu 810E | Jan 2026 | Train+infer; 96GB HBM2e; between A800 and H20; in production |
| Zhenwu M890 | 2026 | 144GB; 800GB/s die-to-die; ~3× 810E |
| Zhenwu V900 | Planned 2027 Q3 | 216GB; 1200GB/s interconnect |
| Zhenwu J900 | Planned 2028 Q3 | Next-gen parallel compute architecture |
2026 commercial metrics: 560K+ cumulative shipments; billion-yuan annualized revenue; 400+ enterprise customers on Zhenwu clusters; registered capital raised to 1B yuan (June 2026); Alibaba pledged 380B yuan over three years for cloud and AI infra. WSJ: new chips CUDA-compatible to ease migration (unlike Huawei's stack). Manufacturing shifting from TSMC toward domestic foundries (industry points to SMIC 7nm-class flows).
04 Why Tech Giants Build Custom AI Chips: Cost, Control, and the Nvidia Tax
AI competition moved from "best model" to "cheapest, most controllable compute."
Five drivers (ranked):
- Economics — inference is rent: Training is down payment; inference is monthly rent. At ChatGPT-scale DAU, inference spend exceeds training. Morgan Stanley cited ~$852M for a 24K Blackwell cluster vs ~$99M for an equivalent TPU cluster (hardware only). SemiAnalysis/Bernstein: custom ASICs can deliver 40–65% TCO advantage over GPUs at scale; 30–40% lower per-token cost for hyperscalers. Nvidia data-center GPU gross margin >70%—in-house silicon converts permanent GPU tax into one-time R&D.
- Supply chain resilience: US export controls on H100/H800/H20; allocation queues even for US buyers. Security here means predictable supply, not just cyber risk.
- Hardware-software co-design: DeepSeek UE8M0 FP8 and MLA; OpenAI Jalapeño tuned for KV cache, batching, latency; Google TPU bound to JAX/TensorFlow. GPUs trade efficiency for flexibility; ASICs do the opposite for known workloads.
- Bargaining power and differentiation: Even partial self-supply strengthens Nvidia negotiations and cloud marketing ("model + cloud + silicon" full stack).
- Energy: Inference ASICs optimize performance per watt—power and cooling rival chip purchase cost at gigawatt-scale datacenters.
| Dimension | Training | Inference |
|---|---|---|
| Workload | Dynamic, experimental | Static, predictable requests |
| Software moat | CUDA (cuDNN, NCCL, Nsight) | Hand-tuned kernels per model |
| Chip goal | Peak FLOPS + programmability | Throughput, latency, $/token |
| Spend pattern | One-time cluster capex | 24/7 opex at larger scale |
| Leaders | Nvidia H100/B200 | TPU, Trainium, Maia, Jalapeño, rumored DeepSeek ASIC |
Bottom line: Training remains Nvidia's home turf; inference is the custom ASIC battleground.
05 Hard Numbers, Risks, and What Could Go Wrong
- DeepSeek funding: ~$7.4B external round (June 2026); disclosed uses include custom AI chips and domestic compute expansion
- T-Head shipments: 560K+ units; billion-yuan annualized revenue (H1 2026)
- ASIC TCO band: 40–65% advantage vs GPUs at multi-year inference scale; 30–40% per-token savings for hyperscalers
- Custom silicon growth: 44.6% vs GPU 16.1% (TrendForce 2026)
- Zhenwu 810E: 96GB HBM2e; performance between Nvidia A800 and H20
- Alibaba infra pledge: 380B yuan over three years (chips, compute, liquid cooling)
Risks:
- Do not state DeepSeek chips are "confirmed" until an official release.
- Meta MTIA already saw a full redesign—architecture shifts can void ASIC bets.
- Foundry geopolitics: SMIC-class flows lag TSMC 3nm on leading-edge AI silicon.
- CUDA compatibility does not equal mature optimization stacks on day one.
06 FAQ, Six-Step Framework, and Wrap-Up
- Q1: Is DeepSeek really building its own AI chip? A: Reuters (July 7, 2026, three sources) reports an early-stage inference chip. No official confirmation.
- Q2: Did Liang Wenfeng announce a chip program? A: No. He cited export controls as the main challenge in 2024—not a product launch.
- Q3: How is Alibaba involved? A: T-Head (2018 Jack Ma strategy) mass-produces Zhenwu chips—560K+ shipped, billion-yuan revenue in 2026.
- Q4: Why inference first? A: Predictable workloads suit ASICs; training still needs CUDA depth.
- Q5: Security or savings? A: Both—economics leads; export controls accelerate an existing trend.
Six steps for engineering teams:
- Chip news radar: Track Reuters, OpenAI blog, Alibaba earnings for DeepSeek confirmation.
- Split train vs infer budgets: Rumored DeepSeek silicon is inference-only—model TCO separately.
- Watch stack signals: UE8M0 FP8, Ascend ports, T-Head CUDA compatibility—migration cost follows software, not press releases.
- API fallback chains: LiteLLM or OpenRouter so supplier shifts do not require app rewrites.
- ASIC lock-in risk: Non-Transformer futures can obsolete fixed-function silicon—keep model flexibility.
- Stable local compute: Run Cursor agents, OpenClaw, and iOS CI on dedicated bare-metal nodes—not shared VPS that stalls when supply chains move.
Primary sources (re-check links before citing in production):
OpenAI: Jalapeño inference chip with Broadcom
Caixin Global: Alibaba Zhenwu 810E analysis
SCMP: Joe Tsai on export restrictions
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